Historically, in semiconductor manufacture, single semiconductor die (or chips) were mounted within a sealed package and such package was then mounted to, for example, a circuit board. In such a manner various functionality or increased capacity could be provided for high level device such as a computer, a cell phone or the like. Which such packages, for example a dual inline package (DIP) or a single inline package (SIP), served to provide protection for the enclosed die from physical damage, contaminants in the surrounding environment and for providing electrical connection of the die to other electrical circuitry, such packages could also be bulky and require that the size of the circuit board or module be large enough to accommodate a plurality of such packages.
To reduce the size required by such singly packaged chips, recent trends have included the development of alternated packaging such a ball grid arrays, flip chips and the like. However, further reductions in size and the ability to provide increased and/or more complex functionality require alternate approaches to die packaging and mounting. One such alternate approach is to eliminate such singular packaging, where possible, and to mount die in multiples, for example as vertically oriented stacks of die. Such mounting in multiples, or stacking, while capable of providing a much reduced footprint compared the use of single packaged die, introduces a need to provide a method, and materials that can be employed by that method, for attaching each die in such a stack, to the adjacent die while also providing access to means for providing electrical contact to each die's circuitry. In addition, such materials used by such methods should also provide a stress buffer function, where they are used to attach such a chip or chip stack to a substrate having a different coefficient of linear expansion, and thus avoid damage to one or more of the chips or the substrate due to fluctuations in the environment.
Such chip stack mounting can also create a need to provide die that are thinned with respect to the original thickness of the wafer from which such die are provided. This thinning process can advantageously be used to keep the chip stack height to a minimum value, and also make it possible to provide through-chip vias that can provide for moving electrical contact from one surface of the die to the other surface. Therefore there is also a need to provide a method, and materials that can be employed by that method, that can be used to bond a substrate, such as a semiconductor wafer, to another substrate that is used in a wafer thinning process. Such material should provide a strong bond and protection for the bonded surface, while also providing for a readily implemented method of release of the wafer, and removal of such bonding material therefrom, after the thinning operation is complete.
It should be noted that while chip stacking is referred to as a recent trend, see published U.S. patent application Ser. No. 2005/0078436, published Jan. 6, 2005 and entitled “Method For Stacking Chips Within A Multichip Module Package,” the use of adhesive materials for attaching semiconductor die (chips) to substrates, die to lead frames or for chip stacking has been a subject of investigation for more than just a few years. For example, at column 3, lines 18-20 of U.S. Pat. No. 5,286,679 issued Feb. 15, 1994 and entitled “Method For Attaching A Semiconductor Die To A Leadframe Using A Patterned Adhesive Layer.” However, despite this long know need, materials and methods that use such materials have not been widely adopted and therefore alternate materials and methods for both chip stacking and wafer thinning are needed.